MO1576

Pb-Free RoHS Compliant
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优点

  • 1 Hz to 2.5MHz ±5 x 10-6 all-inclusive frequency stability
  • Smallest TCXO Footprint: 1.2mm2
    ・1.5 x 0.8 mm CSP / ・No external bypass cap required
  • Ultra-low power: +6 μA (100kHz)
  • Improved stability reduces system power with fewer network timekeeping updates

用途

  • ULP input devices, Proprietary wireless, Sensor interface
  • Smart pens, Health and wellness monitors
  • Smart Meters (AMR)
  • Pulse-per-Second Timekeeping

一般规格

Conditions: Min/Max limits are over temperature, Vdd = +1.8V±10%, unless otherwise stated. Typicals are at +25°C and Vdd = +1.8V.

Item symbol Min. Typ. Max. Unit Condition
Output Frequency f 1 - 2.5M Hz  
Operating Supply Voltage Vdd +1.62 +1.8 +1.98 V  
Operating Temperature T_use -20~+70 / -40~+85 ℃  
Total Frequency Stability[1] F_stab -5.0 - +5.0 ×10-6 All inclusive, Stability code : E.
-20 - +20 All inclusive, Stability code : G.
Allan Deviation AD - 1e-8 4e-8 - 1 second averaging time
First Year Frequency Aging F_aging - ±1.0 - ×10-6 TA = +25°C, Vdd = +1.8V
Supply Current Idd - +3.65 +5 μA Fout = 1 Hz, Vdd = +1.8V, no load
- +4.5 +5.5 Fout = 33 kHz, Vdd = +1.8V, no load
- +6.0 +10 Fout = 100 kHz, Vdd = +1.8V, no load
- +13 +20 Fout = 1 MHz, Vdd = +1.8V, no load
- +33 +40 Fout = 2 MHz, Vdd = +1.8V, no load
Start-up Time at Power-up T_start - 150 300 ms

Fout > 200 Hz.

Measured when supply reaches 90% of final Vdd to the first output pulse and within specified min/max frequency limit.
-

300+

2.0 cycles

300+

2.5 cycles

10 Hz < Fout ≤ 200 Hz.

Measured when supply reaches 90% of final Vdd to the first output pulse and within specified min/max frequency limit.
-  

500+

2.0 cycles

1 Hz ≤ Fout ≤ 10 Hz.

Measured when supply reaches 90% of final Vdd to the first output pulse and within specified min/max frequency limit.
Output Clock Duty Cycle DC 45 - 55 %  
Output Voltage Low VOL - - Vdd x 0.1 V IOL = +50 μA 15pF load
Output Voltage High VOH Vdd x 0.9 - - IOH = -50 μA, 15pF load
Output Rise/Fall Time Tr,Tf - 9.0 20 ns 20-80%, 15 pF Load, Vdd = 1.8 +/- 10%
Integrated Phase Jitter IPJ - 2 3.5 nsRMS f > 1 kHz. Integration bandwidth = 100 Hz to f /2.
Inclusive of +50 mV peak-to-peak sinusoidal noise on Vdd. Noise frequency
100 Hz to 20 MHz.
Period Jitter PJ - 2.2 4.5 nsRMS Cycles = 10,000, f = 100kHz. Per JEDEC standard 65B
Peak-to-Peak Period Jitter PJp-p - 20 35 nsp-p
Packing Unit 1000pcs./reel（φ180）or 3000pcs./reel（φ180）

[1]. Relative to 32.768 kHz, includes initial tolerance, over temp stability, Vdd, load variation, hysteresis, board-level underfill, 3x reflow.
Tested with Keysight 53132A frequency counter. Measured with 100 ms gate time for accurate frequency measurement.

Consult our sales representative for other specifications.

外形尺寸等 (点击看大图)

参考

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